In conventional MOSFETs, the maximum donor concentration [ND] in an n−-type zone and therefore also the electrical conductivity of the n−-type zone are determined by the required blocking capability. In the event of an avalanche breakdown, approximately 1.5×1012 cm−2 donors are then ionized, the countercharge of which is found in the acceptor charge of the p-conducting zone of the MOSFET structure. If a higher donor concentration is to be made possible, countercharges for the donor atoms of the n−-type zone have to be found approximately in the same component plane. In the case of MOS field plate transistors comprising a trench structure, as are known from document U.S. Pat. No. 6,573,558 B2, this is effected by means of the charge carriers of the field plate. In the case of compensation components, such as in the case of “CoolMOS”, which have n−-type zones and p-type zones arranged alternately in cells, this is done by means of acceptors of the p-type zones as countercharges.
In this context, an n−-type or p−-type zone is to be understood as meaning a region of a semiconductor component which is lightly doped and has a defect concentration [ND] or [NP], respectively, of between1×1012 cm−3≦([ND] or [NP])≦1×1017 cm−3where [ND] is the donor concentration and [NP] is the acceptor concentration.
An n-type or p-type zone is to be understood as meaning a region of a semiconductor component which is medium-doped and has a defect concentration of between1×1017 cm−3≦([ND] or [NP])≦1×1018 cm−3.
An n+-type or p+-type zone is to be understood as meaning a region of a semiconductor component which is highly doped and has a defect concentration of between1×1018 cm−3≦([ND] or [NP])≦1×1020 cm−3.
A metallically conducting semiconductor zone is to be understood as meaning a region of a semiconductor component which has an extremely high doping and has a defect concentration of between1×1020 cm−3≦([ND] or [NP])≦1×1022 cm−3.
If the intention is to further improve the electrical conductivity of an n−-type zone in compensation components, such as for example “CoolMOS”, in comparison with the prior art, the degree of compensation has to be set more and more accurately. Even nowadays, this is encountering the limits of technological feasibility. The MOS field plate transistors comprising a trench structure which are known from U.S. Pat. No. 6,73,558 B2 have the disadvantage that, depending on the type of connection of the field plate, the entire reverse voltage is dropped either at the source end or at the drain end with respect to the n−-type zone, and therefore very thick insulation layers are required. At a continuous loading of 600 V, approximately 6 μm thick SiO2 would be required, which significantly reduces the effect of the field plate in providing countercharges.
Further semiconductor components comprising trench structures are known from document U.S. Pat. No. 6,608,350 B2. With trench structures of this type, it is possible to fabricate a high-voltage transistor having a low forward resistance with a lightly doped semiconductor body region on an n+-conducting semiconductor substrate as a result of the trench structure in the lightly doped semiconductor body region, on the top side of the transistors, being completely filled with a dielectric which has a high relative permittivity εr.
Instead of a more precise compensation in the case of “CoolMOS”, the patent applications DE 10 2004 007 197.7 and DE 10 2004 007 196.9 proposed that the counter-charge be provided by means of a trench capacitor having a significantly higher capacitance than the surrounding Si. To create technically or economically attractive use options, the relative permittivity of the insulator with which the trench in the Si is filled would have to be approximately εr≈1000. Given typical trench widths and widths of the n−-type zone in the region of a few μm, on resistance values that are at least a factor of 3 better than in the case of “CoolMOS” at present can be achieved for 600 V components.
Patent application DE 10 2004 044 619.9 discloses a capacitor structure in which the dielectric contains the oxide of the metal of the conducting regions. The stack is produced by multiple application of the metal in each case followed by oxide. However, this process requires a large number of process steps, and consequently there is a high risk of incorrect processing.